The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits), and the like requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Many modern integrated circuit chips may have one or more “logic regions” where primarily logic circuits or logic devices reside and one or more “memory regions or arrays” that primarily contain memory devices. Although the logic devices and memory devices are often formed on the same chip and frequently share common materials, such devices do have fundamental structural differences, and they are often formed at different times during a particular process flow that is performed to form the completed device.
The basic structures of the logic devices and memory devices are fabricated by forming various layers of material and thereafter patterning those layers of material using photolithography and etching processes. Often, this basic layer “stack” for the memory devices is formed prior to fabricating the gate electrode structures for the logic regions of the device. Thus, the process designer is often faced with the challenge of ensuring that process steps employed in the fabrication of one device do not harm other devices that are previously or concurrently fabricated.
Over recent years, there has been a constant drive to reduce the physical size of various consumer electronic products that employ integrated circuits. The demand for smaller consumer products with greater capability has resulted in the scaling or reduction in the physical size of integrated circuit devices that are employed in such consumer products. The reduction in size of the integrated circuits has been achieved by, among other things, reducing the physical size of the various semiconductor devices, e.g., the transistors, and by greatly increasing the density of such transistors in a given area.
With reduction in physical size, however, there is a greater likelihood that the processes employed in the fabrication of one device of the integrated circuit may adversely affect the prior or concurrent fabrication of other devices due to increased proximity of the devices. In one such example, during the polishing of a polycrystalline silicon layer over the memory devices, such as through chemical mechanical polishing (CMP), which as noted above may be formed in part prior to the formation of the logic devices, it is often desirable to prevent any polishing of the same polycrystalline silicon layer from occurring in the logic areas (i.e., areas where logic devices are to be formed), due to certain thickness requirements of the polysilicon layer in the logic areas. Thus, as currently practiced in the art, a protective material layer (typically a silicon oxide material) is deposited over the device, and then removed only from the memory devices, prior to polishing, such that the protective layer remains in place over the logic areas during polishing, which ensures the desired polycrystalline silicon thickness will remain. However, the deposition of the extra protective material layer requires an extra masking and etching step (to remove it from the memory devices) prior to the CMP step. This extra step undesirably increases the time and cost required in the fabrication of the semiconductor device.
Accordingly, it is desirable to provide improved methods for fabricating integrated circuits that reduce the time and cost required for the fabrication process. Additionally, it is desirable to provide methods for fabricating integrated circuits that eliminate the need for the masking and etching of protective layers prior to polishing. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.